Computing Paradigms
A model of computation defines a computational step. An architecture organizes state, control, communication, and execution. A physical embodiment recruits a material process to realize one or more models. They belong in the same survey, but not in the same category.
“Models of Computation” would therefore be too narrow. Compute-in-memory and photonic computing, for example, are not complete formal models merely because they depart from the stored-program machine. “Computing Paradigms” covers models, architectures, and embodiments while keeping those distinctions visible.
The practical question is:
Which alternatives to stored-program, von Neumann-style computation have progressed from formal proposal to physical demonstration, integration, scale, external access, and recurring use?
Status was checked on 2026-08-11. Vendor milestones remain vendor reports unless independently reproduced.
Maturity scale
The matrix uses the same substrate-neutral stages for every family:
- Reference — an executable implementation exposes the semantics, usually on a conventional host.
- Physical — a purpose-built system realizes the relevant primitive rather than merely simulating it.
- Integrated — state, execution, communication, and control form a coherent device or system.
- Scaled — many elements operate through a demonstrated composition or interconnect.
- Access — outsiders can program or run the relevant implementation.
- Operational — it performs recurring work beyond a one-off demonstration.
A mark records the strongest public implementation found. It does not transfer one project’s achievement to every machine using the same label.
Execution models
These families primarily change what causes a computational step.
Scroll horizontally to compare all six stages.
| Paradigm | Reference | Physical | Integrated | Scaled | Access | Operational |
|---|---|---|---|---|---|---|
| Spatial dataflow | ||||||
| Interaction nets | — | — | — | — | ||
| Functional graph reduction | — | — | ||||
| Cellular automata |
“Access” for interaction nets means access to software evaluators, not purpose-built hardware.
Architectural and physical paradigms
These families primarily change where state and work reside, or which physical dynamics perform the operation.
Scroll horizontally to compare all six stages.
| Paradigm | Reference | Physical | Integrated | Scaled | Access | Operational |
|---|---|---|---|---|---|---|
| Neuromorphic and spiking | ||||||
| Compute-in-memory | — | |||||
| Photonic analog computing | — | — | ||||
| Thermodynamic and probabilistic | — | — | ||||
| Reversible and adiabatic | — | — | — | |||
| Quantum computing | ||||||
| Molecular and chemical | — | — |
Evidence and open tests
Each entry uses the same four fields. “Next test” means the result that would materially strengthen or weaken the implementation claim.
Spatial dataflow
- Evidence
- Dataflow graphs, Kahn process networks, and synchronous dataflow have mature software and FPGA toolchains. SambaNova and NextSilicon report operational reconfigurable dataflow processors.
- Embodiments
- CMOS ASICs, FPGAs, systolic arrays, and coarse-grained reconfigurable arrays.
- Boundary
- Irregular control, mutable pointer structures, reconfiguration cost, and dependence on a stored-program host.
- Next test
- A broad workload suite running without application-specific rewriting or a supervisory conventional processor.
Interaction nets
- Evidence
- HVM2 and Vine execute the model on CPUs and GPUs. Tendrils says it is building dedicated hardware, but has disclosed no physical demonstration.
- Embodiments
- Conventional digital processors currently executing a graph-rewriting abstract machine.
- Boundary
- Placement, allocation, routing, reuse, and readback of a dynamically changing graph.
- Next test
- A purpose-built core running nontrivial programs with measured energy, memory, and routing costs.
Functional graph reduction
- Evidence
- Heron is an FPGA processor core for pure non-strict functional languages; HAFLANG continues the hardware line.
- Embodiments
- FPGA fabric and conventional processors.
- Boundary
- Allocation, garbage collection, locality, and dynamically varying parallelism.
- Next test
- A many-core reducer whose end-to-end gains survive allocation, communication, and collection.
Cellular automata
- Evidence
- Universal variants are established, with purpose-built FPGA systems and memristive in-memory demonstrations.
- Embodiments
- FPGA, CMOS, and memristive arrays.
- Boundary
- Compiling ordinary algorithms into local rules while preserving locality; global communication and input/output.
- Next test
- A programmable system where useful algorithms remain local after compilation.
Neuromorphic and spiking
- Evidence
- Intel’s Hala Point integrates 1,152 Loihi 2 processors for research workloads.
- Embodiments
- Digital CMOS, mixed-signal circuits, and emerging memory devices.
- Boundary
- Programming portability, training, numerical comparison, and workload generality.
- Next test
- Independently reproduced gains on tasks whose event structure was not selected to flatter the hardware.
Compute-in-memory
- Evidence
- IBM fabricated a 64-core phase-change-memory inference chip.
- Embodiments
- SRAM, phase-change memory, ReRAM, memristive arrays, and mixed-signal CMOS.
- Boundary
- Conversion overhead, precision, endurance, variability, and incomplete control semantics.
- Next test
- End-to-end gains including conversion, calibration, memory updates, and host coordination.
Photonic analog computing
- Evidence
- A single-chip photonic neural network has integrated optical matrix operations and nonlinear activation.
- Embodiments
- Silicon photonics, lasers, modulators, detectors, and optical memory elements.
- Boundary
- Electronic input/output, precision, nonlinearity, storage, calibration, and thermal stability.
- Next test
- An externally programmable system whose advantage includes electronic interfaces and control.
Thermodynamic and probabilistic
- Evidence
- Extropic reports X0 silicon and the XTR-0 prototype platform. Normal Computing reports a 2025 CN101 tape-out. THRML provides a conventional reference environment.
- Embodiments
- Stochastic CMOS, with magnetic and other noisy devices also under investigation.
- Boundary
- Narrow sampling semantics, calibration, scaling, and limited independent measurement.
- Next test
- Reproducible application-level advantage on externally selected distributions and workloads.
Reversible and adiabatic
- Evidence
- Vaire reports an energy-recovery proof of concept; no externally accessible system has been disclosed.
- Embodiments
- CMOS adiabatic logic, with superconducting implementations also proposed.
- Boundary
- Clock and interconnect losses, area, latency, errors, and incomplete system-level energy accounting.
- Next test
- Net energy recovery at system scale after control, memory, communication, and error handling.
Quantum computing
- Evidence
- Circuit, measurement, and annealing models have physical systems and mature software stacks; IBM reports a decade of cloud-accessible quantum processors.
- Embodiments
- Superconducting circuits, trapped ions, neutral atoms, photons, and annealing systems.
- Boundary
- Error correction, control overhead, data loading, and useful advantage.
- Next test
- A reproducible application advantage including error correction and classical orchestration costs.
Molecular and chemical computing
- Evidence
- Chemical-reaction and strand-displacement calculi have physical realizations, including enzyme-powered DNA computing networks.
- Embodiments
- DNA, enzymes, molecular reactions, and surface-confined systems.
- Boundary
- Latency, reset, error, cascading depth, automation, and electronic readout.
- Next test
- A reusable molecular system executing several nontrivial programs without manual laboratory reconstruction.
Reading the result
A physical demonstration establishes that a primitive can exist. It does not establish programmability, scaling, economy, or superiority. Absence of a custom device does not refute a model; it identifies the next criticism the model has not survived.
The comparison is not about exoticness. The relevant question is whether an advantage survives representation, execution, communication, control, and readout.